Integrated semiconductor memories, for example DRAM (dynamic random access memory) semiconductor memories, have a memory cell array in which memory cells are connected to word lines and bit lines. FIG. 3 shows a simplified illustration of an integrated semiconductor memory device 100 having a memory cell array 10. The memory cell array 10 includes word lines WL and bit lines BL to which memory cells SZ are respectively connected. FIG. 3 shows an example of a DRAM memory cell which includes a selection transistor AT and a storage capacitor SC. To control read and write access to the memory cells in the memory cell array, the memory cell array is actuated by a control circuit 20 on the basis of control signals which are applied to a control connection S20 of the control circuit 20. The integrated semiconductor memory device also includes an address register 30 with an address connection A30 to apply address signals.
To select a memory cell in the memory cell array for read and write access, the address associated with the memory cell is applied to the address register 30 by the address signal ADS. In the event of write access to the memory cell SZ, a write command WR is applied to the control connection S20 of the control circuit 20. The word line WL is then actuated by the control circuit 20 using a signal level which switches the selection transistor AT to an on state, so that the storage capacitor SC is connected at low impedance to the bit line BL via the activated path in the selection transistor. If it is possible to write to the memory cell SZ via the data connection IO1, the appropriate memory information can be written to the memory cell SZ by applying a data signal to the data connection IO1.
For read access to the memory cell SZ, a read command RD is applied to the control connection S20 of the control circuit 20 after the appropriate address signal has been applied to the address register 30. The control circuit 20 then actuates the word line WL again such that the selection transistor AT is turned on. The storage capacitor SC can now be discharged to the bit line BL via the controllable path in the selection transistor. If the bit line BL was charged to a precharge potential before the memory cell SZ was activated, a change in potential from the precharge potential appears on the bit line, depending on the charge state of the storage capacitor SC, and this change in potential is amplified by a sense amplifier and is supplied to the data connection IO1.
FIG. 4A shows a first group 11 of sense amplifiers in a region of the memory cell array 10 in FIG. 1 in an enlarged illustration. For reasons of better clarity, the memory cells SZ1, SZ2, SZ3 and SZ4 are shown at crossing points between the bit lines BLt1, BLt2, BLt3 and BLt4 and a word line WL. The bit lines are in the form of bit line pairs BLt1-BLc1, BLt2-BLc2, BLt3-BLc3 and BLt4-BLc4. Each of the bit line pairs is connected to a respective sense amplifier. The bit line pair BLt1-BLc1 is connected to the sense amplifier SA1, the bit line pair BLt2-BLc2 is connected to the sense amplifier SA2, the bit line pair BLt3-BLc3 is connected to the sense amplifier SA3 and the bit line pair BLt4-BLc4 is connected to the sense amplifier SA4. The sense amplifiers and their connected bit line pairs have the data connections IO1, . . . , IO4 respectively associated with them. In the example in FIG. 4A, the sense amplifier SA1 has the associated data connection IO1, the sense amplifier SA2 has the associated data connection IO2, the sense amplifier SA3 has the associated data connection IO3 and the sense amplifier SA4 has the associated data connection IO4. The sense amplifiers are connected to their associated data connections via circuit components (not shown), such as a secondary sense amplifier. If the memory cell SZ1 is to be read, for example, the sense amplifier SA1 produces a corresponding signal at the data connection IO1. Accordingly, the sense amplifier SA2 produces an output signal at the data connection IO2 when the memory cell SZ2 is read, the sense amplifier SA3 produces an output signal at the data connection IO3 when the memory cell SZ3 is read and the sense amplifier SA4 produces an output signal at the data connection IO4 when the memory cell SZ4 is read.
For read access to a memory cell, all the other memory cells which are connected to the same word line are simultaneously also connected at low impedance to the bit lines which are connected to them. If, by way of example, the memory cell SZ1 is actuated by an appropriate signal level on the word line WL, not only is the selection transistor for the memory cell SZ1 turned on but also the selection transistors for the memory cells SZ2, SZ3 and SZ4 are simultaneously switched to the on state.
For read access to the memory cell SZ1, not just the sense amplifier SA1 is now activated but also further sense amplifiers in addition, however, depending on the form of organization of the semiconductor memory. For the ×4 form of organization, access to a single memory cell, for example, involves the memory information from 4 adjacent memory cells or 4 adjacent bit line pairs being simultaneously output at the data connections. Hence, in FIG. 4A, read access to the memory cell SZ1 involves not just the sense amplifier SA1 being activated but, in addition, the sense amplifiers SA2, SA3 and SA4, which means that besides the memory content of the memory cell SZ1 at the data connection IO1 it is also possible to tap off the memory contents of the memory cells SZ2, SZ3 and SZ4 at the data connections IO2, IO3 and IO4.
In the case of an ×8 form of organization, a further 7 sense amplifiers are activated in addition to the sense amplifier which is connected by its connected bit line to the memory cell which is to be read, which means that signals are produced simultaneously at a total of 8 data connections. Accordingly, in the case of the ×16 form of organization, 16 sense amplifiers are simultaneously activated and hence 16 output signals are produced at 16 data connections.
FIG. 4B shows a further region in the memory cell array 10 with a second group 12 of sense amplifiers from FIG. 1 in an enlarged illustration. The sense amplifiers in the second group are arranged relative to the bit line pairs in a similar manner to the sense amplifiers in the first group. The sense amplifier SA1′ is connected to a bit line pair BLt1′-BLc1′, the sense amplifier SA2′ is connected to a bit line pair BLt2′-BLc2′, the sense amplifier SA3′ is connected to a bit line pair BLt3′-BLc3′ and the sense amplifier SA4′ is connected to a bit line pair BLt4′-BLc4′. Unlike in the first group 11 of sense amplifiers as shown in FIG. 4A, the sense amplifiers in the second group 12 and hence also the bit line pairs are associated with other data connections, however. The memory state of the memory cell SZ1 whose memory content is amplified by the sense amplifier SA1 is read at the data connection IO4 and no longer as in FIG. 4A at the data connection IO1. The sense amplifier SA4 no longer has a signaling connection to the data connection IO4, but rather has a signaling connection to the data connection IO1.
FIGS. 4A and 4B illustrate that the association between the data connections and the sense amplifiers or the bit lines connected to the sense amplifiers differs on the basis of area within the cell array. Such area-based transpositions between data connections and a group of sense amplifiers are generally made to make the layout of the circuit as efficient as possible.
The area-based transposition of sense amplifiers relative to data connections in various groups of sense amplifiers is a problem when the semiconductor memory is tested. Error mechanisms in semiconductor memories are heavily dependent on topology. To reveal particular errors, the memory cell array in a semiconductor memory is therefore described using a particular data topology on the basis of the respective production test. The use of another topology within the same production test can result in the test becoming totally uncritical toward the error mechanism which is actually of interest and as a result errors ultimately not being revealed.
To be able to describe the memory cell array during a function test using a particular data topology which is characteristic of a type of error, the association between the data connections and the sense amplifiers or the bit lines and memory cells in the memory cell array, known as scrambling, needs to be known. This is the only way of allowing particular bit sequences to be applied to the data connections, said bit sequences then resulting in the storage of a desired error-critical data topology within the memory cell array.
Within the physical error analysis for a semiconductor memory, the scrambling is currently verified by deliberately damaging bit lines. When a memory cell which is connected to the damaged bit line is read, not only this memory cell but also further adjacent memory cells are read at the data connections, as described above. If it is assumed that the adjacent memory cells are connected to sound bit lines and sense amplifiers, the correct data value stored in the respective memory cells is produced at all the data connections. At the data connection which is connected to the damaged bit line, however, a data item will be produced which differs from the expected value. By damaging further bit lines within a group of sense amplifiers it is thus possible to establish successively which bit line or which sense amplifier within a group of sense amplifiers is connected to which of the data connections. When the scrambling on a mask is known fully in this way, all the semiconductor memories which have been produced with this mask can be described in a production test using the desired critical data topologies.
The drawback of the current method for verifying the scrambling described is that semiconductor memories become unusable as a result of the deliberate damage to bit lines. Besides the bit lines, the circuit components or metal layers situated above them in the layout are also destroyed. A further drawback is that the method is very time-consuming on account of the deliberate damage to individual structures.